1. Field of the Invention
The present invention relates to a power supply voltage detection circuit.
2. Description of the Related Art
A power supply voltage detection circuit is a circuit outputting some kind of clear level-detection circuit signal when a power supply voltage reaches a certain prescribed voltage or larger, or a circuit outputting some kind of clear level detection signal during only a term having a prescribed power supply voltage or larger, and it is widely installed on a semiconductor device to prevent operation failures due to a low power supply voltage.
FIG. 9 is a circuit diagram showing a configuration example of a power supply voltage detection circuit. Hereinafter, a MOS field-effect transistor will be simply referred to as a transistor. In a P-channel transistor 8, a source is connected to a power supply voltage terminal VDD, a gate is connected to a ground terminal (reference potential terminal), and a drain is connected to a node terminal N11. In an N-channel transistor 9, a source is connected to a drain of an N-channel transistor 10, a gate is connected to the power supply voltage terminal VDD, and a drain is connected to the node terminal N11. In the N-channel transistor 10, a source is connected to the ground terminal, a gate is connected to a node terminal N12, and the drain is connected to the source of the N-channel transistor 9 as described above. It should be noted that the size of the P-channel transistor 8 is preset to have higher resistance value while connected compared to that of the N-channel transistor 9. In an N-channel transistor 17, a gate and a source are connected to the node terminal N12, and a drain is connected to the power supply voltage terminal VDD.
In a P-channel transistor 4, a source is connected to the power supply voltage terminal VDD, and a gate and a drain are connected to a drain of an N-channel transistor 5. In the N-channel transistor 5, a source is connected to the node terminal N12, a gate is connected to the power supply voltage terminal VDD, and a drain is connected to the gate and the drain of the P-channel transistor 4. In an N-channel transistor 6, a source is connected to the ground terminal, and a gate and a drain are connected to the node terminal N12. A node terminal N11 is connected to a power supply voltage detection signal terminal B1 via inverters 12, 14 and 16. The power supply voltage detection signal terminal B1 outputs a power supply voltage detection signal which increases to a high level when a power supply voltage of a prescribed value or higher is detected.
Respective gates of a P-channel transistor 11, an N-channel transistor 13 and a P-channel transistor 15 are connected to respective inputs of the inverters 12, 14 and 16. Drains and sources of the P-channel transistors 11 and 15 are connected to the power supply voltage terminal VDD and the P-channel transistors 11 and 15 serve as capacitors. A drain and a source of the N-channel transistor 13 are connected to the ground terminal and the N-channel transistor 13 serves as a capacitor. The capacitors 11, 13, and 15 serve to delay signal fluctuation of the node terminal N11.
Functions in the power supply voltage detection circuit will be explained when power supply voltage at the power supply voltage terminal VDD is raised from 0 volts to a prescribed power supply voltage level. The power supply voltage terminal VDD and the node terminal N11 are conducting (in a connected state) through the transistor 8 immediately after raising of the power supply voltage, and the voltage at the node terminal N11 is nearly equal to the power supply voltage. At this time, though the transistor 5 is already conducting, the voltage at the node terminal N12 is lower than the power supply voltage by at least the amount of threshold voltage because the node terminal N12 is short-circuited with the drain and the gate of the transistor 4. In addition, though the passage of an electric current to the ground terminal by the transistor 6 raises voltage according to the voltage of the power supply voltage, it does not rise so much as to exceed the threshold voltage of the transistor 10. As a result, the node terminal N11 maintains the power supply voltage as is, and the power supply voltage detection signal terminal B1 stays at a ground level.
Rising of a power supply voltage of the power supply voltage terminal VDD makes the potential of the node terminal N12 further increase, and the potential of the node terminal N12 finally exceeds the threshold voltage of the transistor 10. Then, voltage increase at the power supply voltage terminal VDD by the transistor 8 and voltage drop at the ground terminal by the transistor 10 occur simultaneously in the node terminal N11. However, since the resistance of the transistors 9 and 10 are lower than that of the transistor 8, the voltage of the node terminal N11 finally decreases toward ground. As a result, the power supply voltage detection signal terminal B1 outputs a high-level voltage equal to the power supply voltage. From then on, the voltage of the power supply voltage detection signal terminal B1 follows a power supply voltage level. A power supply voltage at time when the power supply voltage detection signal terminal B1 outputs a power supply voltage detection signal is the voltage of the power supply voltage detection signal.
When the power supply voltage decreases, movement is completely opposite to the case when it increases. In other words, when the voltage of the power supply voltage is decreased to 0 volts from a prescribed value, the power supply voltage is detected at the initial state, the voltage of the power supply voltage detection signal terminal B1 is at a power supply voltage level, and the transistor 10 is in an ON-state. However, when a power supply voltage drops, voltage of the node terminal N12 is lowered at the same time, and finally it becomes equal to or lower than the threshold voltage of the transistor 10 at time of reaching the power supply voltage detection voltage, and the transistor 10 is OFF. As a result, a path to lower the voltage of the node terminal N11 toward ground is disconnected. However, since there is a source supply path from the power supply voltage terminal VDD in the node terminal N11, the node terminal N11 is in a power supply voltage level. As a result, a signal from the power supply voltage detection signal terminal B1 becomes ground level.
In the power supply voltage detection circuit, upon detection of the power supply voltage, a path from the power supply voltage terminal VDD to the ground terminal monitors a power supply voltage level of the power supply voltage terminal VDD until the power supply voltage detection is finished by continuing to pass an electric current through a path passing through the transistors 4, 5 and 6, and a path passing through the transistors 9 and 10. That is, it means that power consumption is always carried out.
FIG. 10 is a circuit diagram showing a configuration example of another power supply voltage detection circuit. The circuit in FIG. 10 is an addition of transistors 23 and 26, and an inverter 37 to the circuit in FIG. 9. In a P-channel transistor 26, a source is connected to the power supply voltage terminal VDD, a gate is connected to the power supply voltage detection signal terminal B1, and a drain is connected to the source of the P-channel transistor 8. In an N-channel transistor 23, a source is connected to the drain and gate of the N-channel transistor 6, a gate is connected to the power supply voltage detection signal terminal B1 via an inverter 37, and a drain is connected to the node terminal N12.
Points of the circuit functions in FIG. 10 different from the circuit functions in FIG. 9 are explained. When a power supply voltage becomes a prescribed value or more, a signal from the power supply voltage detection signal terminal B1 becomes the same value in voltage as the power supply voltage. At this time, the gate voltage of the transistor 26 becomes the same as the power supply voltage. A gate voltage of the transistor 23 gets at the ground level. Accordingly, the transistors 23 and 26 become OFF so that the path between the power supply voltage terminal VDD and the ground terminal is completely disconnected.
As a result, the power supply voltage detection circuit cannot detect the power supply voltage, even when the power supply voltage becomes less than a prescribed value, since the signal from the power supply voltage detection signal terminal B1 follows the power supply voltage level unless electric charges completely come out from the node terminals N11 and N12 which are kept in a floating state by a leakage current. In other words, it means that the power supply voltage detection circuit works only when the power supply voltage rises from 0 volts to a prescribed value. The principle will be explained. In order to monitor a power supply voltage by the power supply voltage detection circuit, it is required that the voltage of the node terminal N12 be adjusted by the power supply voltage so as to control ON/OFF of the transistor 10, and at the same time, that the voltage be always supplied from the power supply voltage terminal VDD into the node terminal N11, and when the transistor 10 is OFF, that the voltage of the node terminal N11 be increased to the power supply voltage level. However, when once a voltage of the power supply voltage detection signal terminal B1 becomes the power supply voltage, the power supply voltage supply path from the power supply voltage terminal VDD is disconnected in the node terminal N11 and the node terminal N11 becomes a floating at a low level, and the node terminal N11 only receives a voltage drop due to a coupling effect proportional to the power supply voltage by the capacitor 11. Accordingly, the node terminal N11 as an input of the inverter 12 is always looked as a low level seen from the power supply voltage level, and a voltage of the power supply voltage detection signal terminal B1 always follows the power supply voltage level without being based on a power supply voltage. In order to solve this problem, it is required that the power supply voltage once become 0 volts and electric charges in the floating node terminals N11 and N12 must completely come out by a leakage current or the like. Furthermore, it is necessary that the voltage of the node terminal N12 should become the threshold voltage of the transistor 10 or less to make the transistor 10 OFF. Note that the node terminal N12 is provided by the transistor 17 with a path to draw the voltage away until the threshold voltage of the transistor 10 is reached.
In a Patent Document 1 below, described is a power-on-reset circuit which can be used to disable functions such as entering to a special test mode during a power up period.
(Patent Document 1) Japanese Patent No. 3571729
The following problems exist in the power supply voltage detection circuit. Though the power supply voltage detection circuit in FIG. 9 can always keep track of a power supply voltage condition, i.e., can always monitor the power supply voltage, the path between the power supply voltage terminal VDD and the ground terminal always comes in a connection state even after the power supply voltage becomes a prescribed value or larger, and electric power is always consumed. This raises a problem from the view point of low power consumption which is sought by semiconductor devices.
In the power supply voltage detection circuit in FIG. 10, since the power supply voltage detection signal disconnects all paths between the power supply voltage terminal VDD and the ground terminal when the power supply voltage first rises from 0 volts, power consumption occurs only at the start of applying the power supply voltage. However, in order to carry out power supply voltage detection again after the power supply voltage is raised, it is necessary that the power supply voltage should once become 0 volts, and electric charges in the floating node terminals N11 and N12 must completely come out, and therefore, it becomes impossible to detect a power supply voltage, for instance, for a state that the power supply voltage is below a prescribed value. Accordingly, if a power supply voltage drops instantaneously to 0 volts during operation of a semiconductor device, the power supply voltage detection circuit cannot detect it, which raises a problem in that measures protecting against, for instance, lowering of the power supply voltage cannot be taken completely.
Generally, when the power supply voltage detection circuit is required in a semiconductor device and the semiconductor device is in some operation while power is on, sometimes there is no practical trouble during standby if the power supply voltage detection circuit is not in operation. A semiconductor device is not always in a power-on, but sometimes, spends a great proportion of time in standby.